Semiconductor devices using resistive elements have been studied and developed, typical examples of which include an ReRAM (Resistive Random Access Memory), a PRAM (Phase Change Memory), and an STT-RAM (Spin Torque Transfer Random Access Memory). Memory element characteristics of an ReRAM, a PRAM, and an STT-RAM are illustrated in FIG. 13 in Japanese Patent Kokai Publication No. 2008-65953A (PTL 2), FIGS. 17 and 18 in Japanese Patent Kokai Publication No. 2008-130166A (PTL 1), and FIG. 4 in Japanese Patent Kokai Publication No. 2008-192274A (PTL 3), respectively.
A memory cell has a resistive element to which data is written by applying a write voltage across the resistive element to cause a current or an electric field. More specifically, the resistance value of the resistive element is changed by the amplitude or polarity of the write voltage. In contrast, the memory cell is read by applying a read voltage across the resistive element, for example, the voltage being smaller than that used for writing. More specifically, data written in the memory cell is read by detecting whether the resistive element has low resistance or high resistance on the basis of the amplitude of the current that flows by the application of the read voltage. This read voltage needs to be sufficiently small so that the data is not rewritten and the resistance value of the resistive element is not changed.
Japanese Patent Kokai Publications Nos. 2002-216482A and 2007-133930A are listed as PTL 4 and PTL 5, respectively.
The following analysis has been given from a viewpoint of embodiments of the present invention.
FIGS. 3 and 4 illustrate an exemplary embodiment of the present invention. Problems with the semiconductor devices according to the related techniques will be described in view of FIGS. 3 and 4. The semiconductor devices according to the related techniques include data line control circuits, one of which is illustrated in FIGS. 22A and 22B as a prototype circuit, in place of data line control circuits 6 in FIG. 3. In FIG. 3, each data line 3 is coupled to a plurality of multiplexers 7. When a memory cell MC is read/written, a single multiplexer 7 is selectively activated for each data line 3. As a result, a single bit line BL is electrically coupled to each data line 3. Since each data line 3 extends for a long distance as illustrated in FIG. 3, each data line 3 has large parasitic capacitance.
FIG. 4 is a circuit diagram of a part of a memory array 8 in FIG. 3. A memory cell MC is arranged at each intersection of a bit line BL and a word line WL. When a memory cell MC is read, VSS is supplied to a source plate SP and a voltage of a read reference signal VREADREF is supplied to a corresponding data line 3. In this way, the voltage of the read reference signal VREADREF is applied across the resistive memory element 2 of the memory cell MC located at the intersection of a selected word line WL and a selected bit line BL.
The following two conditions need to be satisfied to read a memory cell MC at high speed. The first condition is charging a corresponding data line 3 with the voltage of the read reference signal VREADREF at high speed. Since the data lines 3 have large parasitic capacitance, a current drive circuit having a large current drive capability is necessary.
The second condition is acquiring a larger read current by setting a larger voltage as the voltage of the read reference signal VREADREF. However, the voltage of the read reference signal VREADREF needs to be limited so that the resistance value of the corresponding resistive memory element 2 is not changed when the memory cell MC is read. Namely, it is desirable to increase the setting voltage VREADREF to a voltage level that is close to a voltage limit by accurately controlling the charging so that the difference between the voltage limit and the setting voltage VREADREF is small. Thus, in the above charging operation, it is required that the data line 3 be charged up to the setting voltage VREADREF without causing an overshoot and without influencing the resistance value of the resistive memory element 2.
To satisfy the above first and second conditions, a read circuit including a feedback circuit using a differential amplifier is widely used (see FIG. 6 in PTL 3 and FIG. 11 in PTL 1). In addition, FIG. 44B in PTL 4 illustrates a general circuit as a specific circuit of a differential amplifier.
FIGS. 22A and 22B are circuit diagrams of a data line control circuit configured according to the known techniques according to the above PTLs. The data line control circuit includes a read data line drive circuit 243 and a current drive circuit 35. FIG. 228 specifically illustrates internal circuits of the differential amplifier AMP3V and the current drive circuit 35 in FIG. 22A. In FIG. 22A, the read data line drive circuit 243 includes: a feedback circuit 244 including the differential amplifier AMP3V; and an NMOS transistor N1. A data line 3 is coupled to an inverting input terminal of the differential amplifier AMP3V, and a power supply line coupled to the read reference signal VREADREF is coupled to a non-inverting input terminal of the differential amplifier. In addition, an output terminal of the differential amplifier AMP3V is coupled to a gate of the NMOS transistor N1.
When the data line 3 is charged in a read operation, a current drive node 4 is supplied with a high voltage (for example, VDD) by the current drive circuit 35. In addition, the read data line drive circuit 243 performs feedback control to quickly and accurately charge the data line 3 with the voltage of the read reference signal VREADREF.
In contrast, to output data at high speed, many memory cells MC need to be read simultaneously in a single read operation. Once read data is latched in data line control circuits corresponding to a plurality of memory cells MC, the read data can be outputted sequentially to input/output terminals DQ via read/write buses RWBS and an I/O circuit 107 in accordance with a high-speed clock cycle. However, since reading data from memory cells MC requires relatively long time, many memory cells MC need to be read simultaneously in a single read operation.
To increase the number of memory cells MC that are simultaneously read in a single read operation, it is necessary to reduce the number of bit lines BL coupled to each multiplexer 7 and arrange more data lines 3 and data line control circuits at shorter intervals. Namely, the data line control circuits need to be arranged at shorter intervals. However, in the case of the data line control circuit in FIG. 22 according to the related techniques, the differential amplifier AMP3V in the feedback circuit 244 has a complex circuit configuration and includes many elements (see FIG. 22B). Thus, there is a problem that it is difficult to arrange many data line control circuits at shorter intervals.
Therefore, to realize a high-speed read operation, data line control circuits that can be arranged at short intervals are demanded.